FIGS. 1A to 1E are cross-sectional views depicting a known method of manufacturing a p-type MOS transistor. Referring to FIG. 1A, an active region where a MOS transistor is to be formed is defined by forming an isolation layer 110 in an n-type semiconductor substrate 100. Alternatively, instead of the n-type semiconductor substrate 100, a p-type semiconductor substrate may be used. In this case, an n-type well region is formed in the p-type semiconductor substrate. Next, a gate insulating layer pattern 120 and a gate 130 are subsequently formed on the active region of the substrate 100. The active region under the gate 130 substantially serves as a channel region.
Referring to FIG. 1B, to reduce the short channel effect, halo impurity regions 141 are formed in a vicinity of the channel region under the gate 130 by implanting n-type impurities in a tilted direction (the direction of the arrow) with respect to the substrate 100 with a first ion implanting process.
Referring to FIG. 1C, source/drain extension regions 142, that is, lightly doped drain (LDD) regions are formed within the substrate at both sides of the gate 130 by implanting lightly doped p-type impurities in a vertical direction (the direction of the arrow) with respect to the substrate 100 with a second ion implanting process. In some cases, the second ion implanting process may be performed prior to the first ion implanting process. In addition, although not shown in the figure, an oxide layer may be formed as an ion implanting buffer layer on the surface of the substrate 100 prior to performing the second ion implanting process.
Referring to FIG. 1D, gate spacer 150 is formed on both side walls of the gate 130. Next, source/drain regions 143 are formed within the substrate 100 at both sides of the spacer 150 by implanting heavily doped p-type impurities in a vertical direction (the direction of the arrows) with respect to the substrate 100 with a third ion implanting process.
Referring to FIG. 1E, a general silicide process is performed to form metal silicide layers 160 on the source/drain regions 143 and the gate 130.
In the known method of manufacturing a conventional p-type MOS transistor, boron (B) ions have been used as impurities for the third ion implanting process for forming the source/drain regions 143. In addition, after the B ions are implanted, the implanted B ions are diffused by performing a thermal treatment process. However, because it is difficult to effectively control a transient enhanced diffusion (TED) in which the implanted B ions are rapidly diffused during the thermal treatment process, there is a problem in that a threshold voltage is too sharply lowered. In addition, there is another problem in that a short channel effect (SCE) that a punch-through is so easily generated may increase.
Approaches for using halo impurity regions 141 or pocket regions to suppress the short channel effect have been proposed. However, as devices become more highly integrated, the short channel effect becomes more predominant. Therefore, these approaches have a limitation in suppressing the short channel effect.